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LTC1273 LTC1275/LTC1276 12-Bit, 300ksps Sampling A/D Converters with Reference
FEATURES

DESCRIPTIO
Single Supply 5V or 5V Operation 300ksps Sample Rate 75mW (Typ) Power Dissipation On-Chip 25ppm/C Reference Internal Synchronized Clock; No Clock Required High Impedance Analog Input 70dB S/(N + D) and 77dB THD at Nyquist 1/2LSB INL and 3/4LSB DNL Max (A Grade) ESD Protected On All Pins 24-Pin Narrow PDIP and SW Packages Variety of Input Ranges: 0V to 5V (LTC1273) 2.5V (LTC1275) 5V (LTC1276)
The LTC(R)1273/LTC1275/LTC1276 are 300ksps, sampling 12-bit A/D converters that draw only 75mW from single 5V or 5V supplies. These easy-to-use devices come complete with 600ns sample-and-holds, precision references and internally trimmed clocks. Unipolar and bipolar conversion modes provide flexibility for various applications. They are built with LTBiCMOSTM switched capacitor technology. These devices have 25ppm/C (max) internal references. The LTC1273 converts 0V to 5V unipolar inputs from a single 5V supply. The LTC1275/LTC1276 convert 2.5V and 5V respectively from 5V supplies. Maximum DC specifications include 1/2LSB INL, 3/4LSB DNL and 25ppm/C full scale drift over temperature. Outstanding AC performance includes 70dB S/(N + D) and 77dB THD at the Nyquist input frequency of 150kHz. The internal clock is trimmed for 2.7s maximum conversion time. The clock automatically synchronizes to each sample command eliminating problems with asynchronous clock noise found in competitive devices. A high speed parallel interface eases connections to FIFOs, DSPs and microprocessors.
APPLICATIO S

High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Audio and Telecom Processing Spectrum Analysis
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. LTBiCMOS is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
Single 5V Supply, 300ksps, 12-Bit Sampling A/D Converter
LTC1273 ANALOG INPUT 1 A VDD (0V TO 5V) 2 IN VREF NC 3 BUSY AGND 0.1F 4 CS D11 5 RD D10 6 HBEN D9 7 NC D8 8 NC D7 9 D0/8 D6 10 8- OR 12-BIT D1/9 D5 PARALLEL BUS 11 D2/10 D4 12 D3/11 DGND 5V 24 23 22 21 20 19 18 17 16 15 14 13
Effective Bits and Signal to (Noise + Distortion) vs Input Frequency
12 11
0.1F
2.42V VREF OUTPUT
+
10F P CONTROL LINES
+
10F
10 9
EFFECTIVE BITS
8 7 6 5 4 3 2 1 0 10k fSAMPLE = 300kHz 100k INPUT FREQUENCY (Hz) 1M
LTC1273/75/76 * TA01
U
74 68 NYQUIST FREQUENCY 62 56 50
S/(N + D) (dB)
U
U
2M
LTC1273/75/76 * TA02
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LTC1273 LTC1275/LTC1276 ABSOLUTE AXI U RATI GS
Supply Voltage (VDD) .............................................. 12V Negative Supply Voltage (VSS) LTC1275/LTC1276 .................................. - 6V to GND Total Supply Voltage (VDD to VSS) LTC1275/LTC1276 ............................................... 12V Analog Input Voltage (Note 3) LTC1273 .................................... - 0.3V to VDD + 0.3V LTC1275/LTC1276 .............. VSS - 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) LTC1273 ................................................ - 0.3V to 12V LTC1275/LTC1276 ......................... VSS - 0.3V to 12V
PACKAGE/ORDER I FOR ATIO
TOP VIEW AIN VREF AGND D11 D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9 24 VDD 23 NC 22 BUSY 21 CS 20 RD 19 HBEN 18 NC 17 NC 16 D0/8 15 D1/9 14 D2/10 13 D3/11 SW PACKAGE 24-LEAD PLASTIC SO WIDE
ORDER PART NUMBER LTC1273ACN LTC1273BCN LTC1273ACSW LTC1273BCSW
D5 10 D4 11 DGND 12 N PACKAGE 24-LEAD PDIP
TJMAX = 110C, JA = 100C/W (N) TJMAX = 110C, JA = 130C/W (SW)
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
U
U
W
WW
U
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(Notes 1 and 2)
Digital Output Voltage (Note 3) LTC1273 .................................... - 0.3V to VDD + 0.3V LTC1275/LTC1276 .............. VSS - 0.3V to VDD + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1273AC, LTC1273BC, LTC1275AC LTC1275BC, LTC1276AC, LTC1276BC .... 0C to 70C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW AIN VREF AGND D11 D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9 24 VDD 23 VSS 22 BUSY 21 CS 20 RD 19 HBEN 18 NC 17 NC 16 D0/8 15 D1/9 14 D2/10 13 D3/11 SW PACKAGE 24-LEAD PLASTIC SO WIDE
ORDER PART NUMBER LTC1275ACN LTC1275BCN LTC1275ACSW LTC1275BCSW LTC1276ACN LTC1276BCN LTC1276ACSW LTC1276BCSW
D5 10 D4 11 DGND 12 N PACKAGE 24-LEAD PDIP
TJMAX = 110C, JA = 100C/W (N) TJMAX = 110C, JA = 130C/W (SW)
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LTC1273 LTC1275/LTC1276
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. With Internal Reference (Notes 5 and 6)
LTC1273A/LTC1275A/LTC1276A MIN TYP MAX 12 1/2 1/2 3/4 3/4 1 3 4 10 5 35 LTC1273B/LTC1275B/LTC1276B MIN TYP MAX 12 1 1 1 1 1 4 6 15 10 45 UNITS Bits LSB LSB LSB LSB LSB LSB LSB LSB ppm/C
Differential Linearity Error Offset Error Gain Error Gain Error Tempco
DY A IC ACCURACY (Note 5)
SYMBOL THD PARAMETER Total Harmonic Distortion Up to 5th Harmonic Peak Harmonic or Spurious Noise IMD Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth (S/(N + D) 68dB) CONDITIONS 50kHz/150kHz Input Signal 50kHz/150kHz Input Signal 50kHz/150kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX 72/70 - 83/- 74 - 85/- 76 - 80 4.5 200 UNITS dB dB dB dB MHz kHz S/(N + D) Signal-to-Noise Plus Distortion Ratio
The A ALOG atI T PUT (Note denotes the specifications which apply over the full operating temperature range, otherwise specfications are = 25C. 5)
A
SYMBOL PARAMETER VIN Analog Input Range (Note 9)
IIN CIN tACQ
Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation CONDITIONS IOUT = 0 IOUT = 0 4.95V VDD 5.25V - 5.25V VSS - 4.95V 0V |IOUT| 1mA
The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. (Note 5)
LTC1273A/LTC1275A/LTC1276A MIN TYP MAX 2.400 2.420 5 0.01 0.01 2 2.440 25 LTC1273B/LTC1275B/LTC1276B MIN TYP MAX 2.400 2.420 10 0.01 0.01 2 2.440 45 UNITS V ppm/C LSB/V LSB/V LSB/mA
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U
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U
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(Note 7) Commercial Military Commercial Military (Note 8)

IOUT(REFERENCE) = 0
U
CONDITIONS 4.95V VDD 5.25V (LTC1273) 4.75V VDD 5.25V, - 5.25V VSS - 2.45V (LTC1275) 4.95V VDD 5.25V, - 5.25V VSS - 4.95V (LTC1276) CS = High Between Conversions (Sample Mode) During Conversions (Hold Mode) Commercial Military

LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS 0 to 5 2.5 5 1 50 5 600 1000 V V V A pF pF ns ns
U
3
LTC1273 LTC1275/LTC1276 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage VDD = 4.95V IO = - 10A IO = - 200A VDD = 4.95V IO = 160A IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.95V VIN = 0V to VDD

The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. (Note 5)
LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS 2.4 0.8 10 5 4.7
VOL
Low Level Output Voltage
IOZ COZ ISOURCE ISINK
High Z Output Leakage D11-D0/8 High Z Output Capacitance D11-D0/8 Output Source Current Output Sink Current
The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. (Note 5)
LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS 4.95 4.75 - 2.45 - 4.95
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD ISS PD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) PARAMETER Maximum Sampling Frequency
The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. See Timing Characteristics Figures (Note 5)
LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS

tCONV t1 t2
Conversion Time CS to RD Setup Time RD to BUSY Delay
4
UW
U
U
V V A pF V V V V A pF mA mA
4.0 0.05 0.10

0.4 10 15
- 10 10
CONDITIONS LTC1273/LTC1276 (Notes 10, 11) LTC1275 (Note 10) LTC1275 (Note 10) LTC1276 (Notes 10, 11) LTC1275/LTC1276
5.25 5.25 - 5.25 - 5.25 15 0.065 75 25 0.200
V V V V mA mA mW
UW
CONDITIONS (Note 10) Commercial Military Commercial Military CL = 50pF Commercial Military
300 250 2.7 3.0 0 80 190 230 270
kHz kHz s s ns ns ns ns

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LTC1273 LTC1275/LTC1276
TI I G CHARACTERISTICS
SYMBOL PARAMETER t3 Data Access Time After RD
The denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. See Timing Characteristics Figures (Note 5)
LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS 40

t4 t5 t6
t7
t8 t9 t10 t11
t12
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS (ground for LTC1273) or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS (ground for LTC1273) or above VDD without latch-up. Note 4: When these pin voltages are taken below VSS (ground for LTC1273) they will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS (ground for LTC1273) without latch-up. These pins are not clamped to VDD. Note 5: VDD = 5V (VSS = - 5V for LTC1275/LTC1276), 300kHz at 70C and 250kHz at 125C, tr = tf = 5ns unless otherwise specified.
UW
CONDITIONS CL = 20pF Commercial Military CL = 100pF Commercial Military
90 110 120 125 150 170
ns ns ns ns ns ns ns ns
50

RD Pulse Width CS to RD Hold Time Data Setup Time After BUSY Commercial Military Bus Relinquish Time Commercial Military HBEN to RD Setup Time HBEN to RD Hold Time Delay Between RD Operations Delay Between Conversions (Note 10) Commercial Military
t3 0 40 70 90 100 75 85 90

ns ns ns ns ns ns ns ns ns ns ns ns
20 20 20 0 0 40 500 600 1000
30
Aperture Delay of Sample-and-Hold
25
ns
Note 6: Linearity, offset and full scale specifications apply for unipolar and bipolar modes. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset (LTC1275/LTC1276) is the different voltage measured from - 0.5LSB when the LTC1275/LTC1276 output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note11: AIN must not exceed VDD or fall below VSS by more than 50mV for specified accuracy. Therefore the minimum supply voltage for the LTC1273 is + 4.95V. The minimum supplies for the LTC1275 are +4.75V and - 2.45V and the minimum supplies for the LTC1276 are 4.95V.
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LTC1273 LTC1275/LTC1276
TI I G CHARACTERISTICS (Note 5)
Slow Memory Mode, Parallel Read Timing Diagram
CS
RD
t2
tCONV
t6
t7
BUSY
t3
DATA
HOLD
t12
TRACK
6
UW
ROM Mode, Parallel Read Timing Diagram
CS
t1
t5
t10
t1
t1
t4
t2
t5
t1
t4
t5
RD
t11
t11
tCONV
t2
tCONV
BUSY
t3
DATA HOLD
LTC1273/75/76 * TA03
t7
OLD DATA DB11 TO DB0
t3
t7
NEW DATA DB11 TO DB0
OLD DATA DB11 TO DB0
NEW DATA DB11 TO DB0
t12
t12
TRACK
LTC1273/75/76 * TA04
Slow Memory Mode, Two Byte Read Timing Diagram
HBEN
t8
CS
t9
t8
t9
t1
RD
t5
t1
t4
t5
t2
BUSY
t10
tCONV
t6
OLD DATA DB7 TO DB0
t11
t10
t3
DATA HOLD TRACK
t7
NEW DATA DB7 TO DB0
t3
t7
NEW DATA DB11 TO DB8
t12
t12
LTC1273/75/76 * TA05
ROM Mode, Two Byte Read Timing Diagram
HBEN
t8
t9
t8
t9
t8
t9
CS
t1
t4
t2
t5
t1
t4
t11
t5
t10
t1
t4
t2
t5
RD
tCONV
t7
BUSY
t3
t3
t7
t3
t7
DATA HOLD TRACK
t12
OLD DATA DB7 TO DB0
NEW DATA DB11 TO DB8
t12
NEW DATA DB7 TO DB0
LTC1273/75/76 * TA06
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LTC1273 LTC1275/LTC1276
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
1.0 1.0
SUPPLY CURRENT (mA)
0.5
DNL ERROR (LSB)
INL ERROR (LSB)
0
-0.5
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
LTC1273/75/76 * TPC01
ENOBs and S/(N + D) vs Input Frequency
12 11 10 9 8 7 6 5 4 3 2 1 fSAMPLE = 300kHz 0 10k 100k INPUT FREQUENCY (Hz) 74 68
SIGNAL-TO-NOISE RATIO (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
EFFECTIVE NUMBER OF BITS
LTC1273/75/76 * TPC04
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0 fSAMPLE = 300kHz -20 -40 -60 -80 -100 -120 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M DGND (VRIPPLE = 0.1V) VDD (VRIPPLE = 1mV)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough vs Ripple Frequency (LTC1273)
UW
1M 2M
Differential Nonlinearity
25
Supply Current vs Temperature
20
0.5
15
0
10
-0.5
5
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
LTC1273/75/76 * TPC02
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
LTC1273/75/76 * TPC03
Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency
80 70 60 50 40 30 20 10 fSAMPLE = 300kHz 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M
Distortion vs Input Frequency
0
-10
fSAMPLE = 300kHz THD 2nd HARMONIC 3rd HARMONIC
62 56 50
-20
-30
S/(N + D) (dB)
-40
-50
-60
-70
-80
-90
-100 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
LTC1273/75/76 * TPC05
LTC1273/75/76 * TPC06
Power Supply Feedthrough vs Ripple Frequency (LTC1275/76)
0 fSAMPLE = 300kHz -20 -40 -60 -80 -100 -120 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M VDD (VRIPPLE = 1mV) DGND (VRIPPLE = 0.1V) VSS (VRIPPLE = 10mV)
LTC1273/75/76 * TPC07
LTC1273/75/76 * TPC08
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LTC1273 LTC1275/LTC1276
TYPICAL PERFOR A CE CHARACTERISTICS
Intermodulation Distortion Plot
0 -20
AMPLITUDE (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
fSAMPLE = 300kHz fIN1 = 29.37kHz fIN2 = 32.446kHz ACQUISITION TIME (ns)
-40 -60 -80 -100 -120 0 20 40
60 80 100 120 140 160 FREQUENCY (kHz)
LTC1273/75/76 * F05
Spurious Free Dynamic Range vs Input Frequency
0
SPURIOUS FREE DYNAMIC RANGE (dB)
2.435
-10 -20 -30 -40 -50 -60 -70 -80 -90
fSAMPLE = 300kHz
2.430
REFERENCE VOLTAGE (V)
-100 10k
PI FU CTIO S
AIN (Pin 1): Analog Input. 0V to 5V (LTC1273), 2.5V (LTC1275) or 5V (LTC1276). VREF (Pin 2): +2.42V Reference Output. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic). AGND (Pin 3): Analog Ground. D11-D4 (Pins 4 to 11): Three-State Data Outputs. DGND (Pin 12): Digital Ground. D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs. NC (Pins 17 and 18): No Connection. HBEN (Pin 19): High Byte Enable Input. This pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (D7-D0/8). See Table 1. HBEN also disables conversion start when HIGH. RD (Pin 20): READ Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables the output drivers when CS is low. CS (Pin 21): The CHIP SELECT Input must be low for the ADC to recognize RD and HBEN inputs. BUSY (Pin 22): The BUSY Output shows the converter status. It is low when a conversion is in progress.
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Acquisition Time vs Source Impedance
4500 4000 3500 3000 2500 2000 1500 1000 500 0 10 100 1k RSOURCE () 10k
80 70 60
S/(N + D) vs Input Frequency and Amplitude
fSAMPLE = 300kHz VIN = 0dB VIN = -20dB 50 40 30 20 10 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M VIN = -60dB
LTC1273/75/76 * TPC10
LTC1273/75/76 * TPC11
Reference Voltage vs Load Current
2.425 2.420 2.415 2.410 2.405
100k 1M INPUT FREQUENCY (Hz)
10M
-5
-4
-3 0 -2 -1 LOAD CURRENT (mA)
1
2
LTC1273/75/76 * TPC12
LTC1273/75/76 * TPC13
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LTC1273 LTC1275/LTC1276
PI FU CTI
VSS (Pin 23): Negative Supply. - 5V for LTC1275/ LTC1276. Bypass to AGND with 0.1F ceramic. NC (Pin 23): No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW
Pin 4 MNEMONIC* HBEN = LOW HBEN = HIGH D11 DB11 DB11 Pin 5 D10 DB10 DB10 Pin 6 D9 DB9 DB9 Pin 7 D8 DB8 DB8 Pin 8 D7 DB7 LOW Pin 9 D6 DB6 LOW Pin 10 D5 DB5 LOW Pin 11 D4 DB4 LOW Pin 13 D3/11 DB3 DB11 Pin 14 D2/10 DB2 DB10 Pin 15 D1/9 DB1 DB9 Pin 16 D0/8 DB0 DB8
*D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
FU TIO AL BLOCK DIAGRA
CSAMPLE
SAMPLE AIN HOLD
VREF(OUT)
12-BIT CAPACITIVE DAC 2.42V REFERENCE AGND DGND
INTERNAL CLOCK
TEST CIRCUITS
Load Circuits for Access Time
5V 3k
DBN
DBN
3k
DGND
CL
CL
DGND B) HIGH-Z TO VOL (t3) AND VOH TO VOL (t6)
1273/75/76 * TA07
A) HIGH-Z TO VOH (t3) AND VOL TO VOH (t6)
+
-
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S
VDD (Pin 24): Positive Supply, 5V. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic).
SAMPLE VDD COMPARATOR VSS (NC ON LTC1273)
D11 12 SUCCESSIVE APPROXIMATION REGISTER 12 OUTPUT LATCHES * * * D0/8 BUSY CONTROL LOGIC CS RD HBEN
LTC1273/75/76 * FBD
Load Circuits for Output Float Delay
5V 3k
DBN
3k
DBN
10pF DGND A) VOH TO HIGH-Z
10pF
DGND B) VOL TO HIGH-Z
1273/75/76 * TA08
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LTC1273 LTC1275/LTC1276
APPLICATI
S I FOR ATIO
CONVERSION DETAILS The LTC1273/LTC1275/LTC1276 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel or 2-byte output. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquire phase, and the comparator offset is nulled by the feedback switch. In this acquire phase, a minimum delay of 600ns will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
SAMPLE
AIN
-
HOLD CDAC DAC
AMPLITUDE (dB)
SAMPLE
CSAMPLE
SI
-40 -60 -80
+
COMPARATOR S A R
VDAC
LTC1273/75/76 * F01
12-BIT LATCH
Figure 1. AIN Input
10
U
capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the AIN are loaded into the 12-bit output latches. DYNAMIC PERFORMANCE The LTC1273/LTC1275/LTC1276 have an exceptionally high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to characterize the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1275 FFT plot. Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 300kHz sampling rate and a 29kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 150kHz.
0 -20 fSAMPLE = 300kHz fIN = 29.37kHz -100 -120 0 20 40 60 80 100 120 140 160 FREQUENCY (kHz)
LTC1273/75/76 * F02
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Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot
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LTC1273 LTC1275/LTC1276
APPLICATI S I FOR ATIO U
quency is shown in Figure 4. The LTC1273/LTC1275/ LTC1276 have good distortion performance up to Nyquist and beyond.
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
-10
fSAMPLE = 300kHz THD 2nd HARMONIC 3rd HARMONIC
Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) - 1.76]/6.02 where N is the Effective Number of Bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 300kHz the LTC1273/LTC1275/LTC1276 maintain very good ENOBs up to the Nyquist input frequency of 150kHz. Refer to Figure 3.
12 11 10 9
EFFECTIVE BITS
8 7 6 5 4 3 2 1 0 10k fSAMPLE = 300kHz 100k INPUT FREQUENCY (Hz) 1M
LTC1273/75/76 * F03
Figure 3. Effective Bits and Signal to (Noise + Distortion) vs Input Frequency
Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20log
V22 + V32 + V42 ... + VN2 V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD versus input fre-
W
U
UO
-20
-30
-40
-50
-60
-70
-80
-90
74 68 62 56 50
S/(N + D) (dB)
-100 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
LTC1273/75/76 * F04
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa - fb) while the 3rd order IMD terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula:
IMD (fa fb) = 20log Amplitude at (fa fb) Amplitude at fa
2M
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LTC1273 LTC1275/LTC1276 APPLICATI
0 -20
AMPLITUDE (dB)
S I FOR ATIO
Figure 5 shows the IMD performance at a 30kHz input.
fSAMPLE = 300kHz fIN1 = 29.37kHz fIN2 = 32.446kHz
-40 -60 -80 -100 -120 0 20 40
60 80 100 120 140 160 FREQUENCY (kHz)
LTC1273/75/76 * F05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1273/LTC1275/LTC1276 have been designed to optimize input bandwidth, allowing ADCs to undersample input signals with frequencies above the converters' Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The analog inputs of the LTC1273/LTC1275/LTC1276 are easy to drive. They draw only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During conversion the analog input draws no current. The only requirement is that the amplifier driving
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the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles in 600ns to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADCs' AIN input include the LT1190/LT1191, LT1007, LT1220, LT1223 and LT1224 op amps. The analog input tolerates source resistance very well. Here again, the only requirement is that the analog input must settle before the next conversion starts. For larger source resistance, full DC accuracy can be obtained if more time is allowed between conversions. For more information, see the Acquisition Time vs Source Resistance curve in the Typical Performance Characteristics section. For optimum frequency domain performance [e.g., S/(N + D)], keep the source resistance below 100. Internal Reference The LTC1273/LTC1275/LTC1276 have an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.42V. It is internally connected to the DAC and is available at pin 2 to provide up to 1mA current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10F tantalum in parallel with a 0.1F ceramic). In the LTC1275, the VREF pin can be driven above its normal value with a DAC or other means to provide input span adjustment or to improve the reference temperature drift. Figure 6 shows an LT1006 op amp driving the
INPUT RANGE 1.033VREF(OUT)
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LT1006
VREF(OUT) 2.45V 3 10F
LTC1275 AIN VREF AGND
LTC1273/75/76 * F06
-
Figure 6. Driving the VREF with the LT1006 Op Amp
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APPLICATI S I FOR ATIO U
111...111 111...110 111...101
OUTPUT CODE
reference pin. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should be driven to no more than 4.8V to keep the input span within the 5V supplies. In the LTC1273/ LT1276, the input spans are 0V to 5V and 5V respectively with the internal reference. Driving the reference is not recommended on the LTC1273/LTC1276 since the input spans will exceed the supplies and codes will be lost at full scale. Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1275. This will provide an improved drift (equal to the maximum 5ppm/C of the LT1019A-2.5) and a 2.582V full scale.
INPUT RANGE 2.58V
5V VIN VOUT LT1019A-2.5 GND 3 10F
OUTPUT CODE
Figure 7. Supplying a 2.5V Reference Voltage to the LTC1275 with the LT1019A-2.5
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT Figure 8 shows the ideal input/output characteristics for the LTC1273. The code transitions occur midway between successive integer LSB values (i.e., 1/2LSB, 1 1/2LSBs, 2 1/2LSBs, ... FS - 1 1/2LSBs). The output code is natural binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure 9 shows the input/output transfer characteristics for the LTC1275/LTC1276 in 2's complement format. As stated in the figure, 1LSB for LTC1275/LTC1276 are 1.22mV and 2.44mV respectively. Unipolar Offset and Full Scale Adjustment (LTC1273) In applications where absolute accuracy is important, offset and full scale errors can be adjusted to zero. Figure 10a shows the extra components required for full scale error adjustment. If both offset and full scale adjustments are needed, the circuit in Figure 10b can be used. Offset
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1LSB = FS = 5V 4096 4096
111...100
000...011 000...010 000...001 000...000 0V
UNIPOLAR ZERO
1 LSB INPUT VOLTAGE (V)
FS - 1LSB
LTC1273/75/76 * F08
Figure 8. LTC1273 Unipolar Transfer Characteristic
LTC1275 AIN VREF AGND
LTC1273/75/76 * F07
011...111
011...110
BIPOLAR ZERO
000...001 000...000
111...111 111...110
111...110 100...001 100...000
-FS/2
FS = 5V (LTC1275) FS = 10V (LTC1276) 1LSB = FS/4096
-1 0V 1 LSB LSB INPUT VOLTAGE (V)
FS/2 - 1LSB
LTC1273/75/76 * F09
Figure 9. LTC1275/LTC1276 Bipolar Transfer Characteristic
R1 50 V1
+
A1 AIN R4 100 LTC1273 LTC1275 LTC1276
-
R2 10k R3 10k
FULL SCALE ADJUST AGND
LTC1273/75/76 * F10a
ADDITIONAL PINS OMITTED FOR CLARITY 20LSB TRIM RANGE
Figure 10a. Full Scale Adjust Circuit
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LTC1273 LTC1275/LTC1276
APPLICATI
ANALOG INPUT 0V TO 5V 5V R9 20 R1 10k R2 10k 10k
S I FOR ATIO
+
AIN
-
R4 100k R5 4.3k FULL SCALE 5V ADJUST R3 100k R7 100k R6 400 LTC1273
R8 LTC1273/75/76 * F10b 10k OFFSET ADJUST
Figure 10b. LTC1273 Offset and Full Scale Adjust Circuit
should be adjusted before full scale. To adjust offset, apply 0.61mV (i.e., 1/2LSB) at the input and adjust the offset trim until the LTC1273 output code flickers between 0000 0000 0000 and 0000 0000 0001. To adjust full scale, apply an analog input of 4.99817V (i.e., FS - 1 1/2LSBs or last code transition) at the input and adjust the full scale trim until the LTC1273 output code flickers between 1111 1111 1110 and 1111 1111 1111. It should be noted that if negative ADC offsets need to be adjusted or if an output swing to ground is required, the op amp in Figure 10b requires a negative power supply. Bipolar Offset and Full Scale Adjustment (LTC1275/LTC1276) Bipolar offset and full scale errors are adjusted in a similar fashion to the unipolar case. Figure 10a shows the extra components required for full scale error adjustment. If both offset and full scale adjustments are needed, the circuit in Figure 10c can be used. Again, bipolar offset must be adjusted before full scale error. Bipolar offset adjustment is achieved by trimming the offset adjustment of Figure 10c while the input voltage is 1/2LSB below ground. This is done by applying an input voltage of - 0.61mV or - 1.22mV (- 0.5LSB for LTC1275 or LTC1276) to the input in Figure 10c and adjusting R8 until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For full scale adjustment, an input voltage of 2.49817V or 4.99636V (FS - 1 1/2LSBs for LTC1275 or
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ANALOG INPUT 2.5V (LTC1275) 5V (LTC1276) R1 10k R2 10k
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AIN
-
R4 100k R5 4.3k FULL SCALE 5V ADJUST R3 100k R7 100k R6 200 LTC1275 LTC1276
R8 LTC1273/75/76 * F10c 20k OFFSET ADJUST -5V
Figure 10c. LTC1275/LTC1276 Offset and Full Scale Adjust Circuit
LTC1276) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. BOARD LAYOUT AND BYPASSING The LTC1273/LTC1275/LTC1276 are easy to use. To obtain the best performance from the devices a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. The analog input should be screened by AGND. High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in Figure 11. For the LTC1275/LTC1276 a 0.1F ceramic provides adequate bypassing for the VSS pin. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Noise: Input signal leads to AIN and signal return leads from AGND (Pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an
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LTC1273 LTC1275/LTC1276
APPLICATI
S I FOR ATIO
1 AIN AGND 3
ANALOG INPUT CIRCUITRY
+ -
VREF 2 10F 0.1F 10F
ANALOG GROUND PLANE
LTC1273/75/76 * F11
Figure 11. Power Supply Grounding Practice
error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. A single point analog ground plane separate from the logic system ground should be established at Pin 3 (AGND) or as close as possible to the ADC, as shown in Figure 11. Pin 12 (DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the width for these traces should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion results. These errors are due to feedthrough from the microprocessor to the ADC. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. DIGITAL INTERFACE The ADCs are designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. The HBEN input serves as a data byte select for 8-bit processors and is normally either connected to the microprocessor address bus or grounded.
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LTC1273 VDD 24 0.1F DGND 12 GROUND CONNECTION TO DIGITAL CIRCUITRY DIGITAL SYSTEM
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Internal Clock These ADCs have an internal clock that eliminates the need for synchronization between an external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 2.45s, and a maximum conversion time over the full operating temperature range of 2.7s. No external adjustments are required and, with the guaranteed maximum acquisition time of 600ns, throughput performance of 300ksps is assured. Timing and Control Conversion start and data read operations are controlled by three digital inputs: HBEN, CS and RD. Figure 12 shows the logic structure associated with these inputs. The three signals are internally gated so that a logic "0" is required
LTC1273/75/76 HBEN 19 CS 21 RD 20 CLEAR D FLIP FLOP Q BUSY CONVERSION START (RISING EDGE TRIGGER)
ACTIVE HIGH ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS D11....D0/8 = DB11....DB0 ENABLE THREE-STATE OUTPUTS D11....D8 = DB11....DB8 D7....D4 = LOW D3/11....D0/8 = DB11....DB8
LTC1273/75/76 * F12
* D11....D0/8 ARE THE ADC DATA OUTPUT PINS DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
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APPLICATI S I FOR ATIO U
8MSBs) where it can be read in two read cycles. The 4MSBs always appear on D11...D8 whenever the threestate output drivers are turned on. Slow Memory Mode, Parallel Read (HBEN = LOW) Figure 13 and Table 2 show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low trigger a conversion and the ADC acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs D11...D0/8. Slow Memory Mode, Two Byte Read For a two byte read, only 8 data outputs D7...D0/8 are used. Conversion start procedure and data output status for the first read operation are identical to Slow Memory Mode, Parallel Read. See Figure 14 timing diagram and Table 3 data bus status. At the end of the conversion, the low data byte (D7...D0/8) is read from the ADC. A second READ operation, with the HBEN high, places the high byte on data outputs D3/11...D0/8 and disables conversion start. Note
t5 t10 t1 t11 t6 OLD DATA DB11-DB0 t12 t7 NEW DATA DB11-DB0
LTC1273/75/76 * F13
on all three inputs to initiate a conversion. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress. There are two modes of operation as outlined by the timing diagrams of Figures 13 to 16. Slow Memory Mode is designed for microprocessors which can be driven into a WAIT state. A READ operation brings CS and RD low which initiates a conversion and data is read when conversion is complete. The second is the ROM Mode which does not require microprocessor WAIT states. A READ operation brings CS and RD low which initiates a conversion and reads the previous conversion result. Data Format The output format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justified (i.e., LSB is the most right-hand bit in a 16-bit word). For a two byte read, only data outputs D7...D0/8 are used. Byte selection is governed by the HBEN input which controls an internal digital multiplexer. This multiplexes the 12-bits of conversion data onto the lower D7...D0/8 outputs (4MSBs or
CS t1 RD t2 BUSY t3 DATA HOLD TRACK tCONV
Figure 13. Slow Memory Mode, Parallel Read Timing Diagram
Table 2. Slow Memory Mode, Parallel Read Data Bus Status
Data Outputs Read D11 DB11 D10 DB10 D9 DB9 D8 DB8 D7 DB7 D6 DB6 D5 DB5 D4 DB4 D3/11 DB3 D2/10 DB2 D1/9 DB1 D0/8 DB0
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LTC1273 LTC1275/LTC1276
APPLICATI
HBEN t8 CS t1 RD t2 BUSY t3 DATA HOLD TRACK
LTC1273/75/76 * F14
S I FOR ATIO
t CONV t6 OLD DATA DB7-DB0 t7 NEW DATA DB7-DB0
t12
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs First Read Second Read D7 DB7 Low D6 DB6 Low D5 DB5 Low D4 DB4 Low D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 DB1 DB9 D0/8 DB0 DB8
that the 4MSBs appear on data output D11...D8 during both READ operations. ROM Mode, Parallel Read (HBEN = LOW) The ROM Mode avoids placing a microprocessor into a WAIT state. A conversion is started with a READ operation, and the 12 bits of data from the previous conversion are available on data outputs D11...D0/8 (see Figure 15 and Table 4). This data may be disregarded if not required. A second READ operation reads the new data (DB11...DB0) and starts another conversion. A delay at least as long as the ADC's conversion time plus the 600ns minimum delay between conversions must be allowed between READ operations. ROM Mode, Two Byte Read As previously mentioned for a two byte read, only data outputs D7...D0/8 are used. Conversion is started in the
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normal way with a READ operation and the data output status is the same as the ROM mode, Parallel Read (see Figure 16 timing diagram and Table 5 data bus status). Two more READ operations are required to access the new conversion result. A delay equal at the ADCs' conversion time must be allowed between conversion start and the third data READ operation. The second READ operation with HBEN high disables conversion start and places the high byte (4MSBs) on data outputs D3/11...D0/8. A third read operation accesses the low data byte (DB7...DB0) and starts another conversion. The 4MSBs appear on data outputs D11...D8 during all three read operations. MICROPROCESSOR INTERFACING The LTC1273/LTC1275/LTC1276 allow easy interfacing to digital signal processors as well as modern high speed, 8-bit or 16-bit microprocessors. Here are several examples.
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APPLICATI S I FOR ATIO
CS t1 RD t2 BUSY t3 DATA HOLD TRACK
LTC1273/75/76 * F15
t4
OLD DATA DB11-DB0 t12
Figure 15. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW) Table 4. ROM Mode, Parallel Read Data Bus Status
Data Outputs First Read (Old Data) Second Read D11 DB11 DB11 D10 DB10 DB10 D9 DB9 DB9 D8 DB8 DB8 D7 DB7 DB7 D6 DB6 DB6 D5 DB5 DB5 D4 DB4 DB4 D3/11 DB3 DB3 D2/10 DB2 DB2 D1/9 DB1 DB1 D0/8 DB0 DB0
HBEN t8 CS t1 RD t2 BUSY t3 DATA HOLD TRACK t12 OLD DATA DB7-DB0 t7 t3 NEW DATA DB11-DB8 t12 t7 t3 t7 NEW DATA DB7-DB0 t11 tCONV t4 t5 t1 t4 t5 t10 t2 t1 t4 t5 t9 t8 t9 t8 t9
Figure 16. ROM Mode Two Byte Read Timing Diagram Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs First Read (Old Data) Second Read (New Data) Third Read (New Data) D7 DB7 Low DB7 D6 DB6 Low DB6 D5 DB5 Low DB5 D4 DB4 Low DB4 D3/11 DB3 DB11 DB3 D2/10 DB2 DB10 DB2 D1/9 DB1 DB9 DB1 D0/8 DB0 DB8 DB0
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t5 t1 t4 t5 t11 t CONV t7 t2 t CONV t3 NEW DATA DB11-DB0 t12 t7
LTC1272 * TA16
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APPLICATI
TMS320C25
S I FOR ATIO
Figure 17 shows an interface between the LTC1273 and the TMS320C25. The W/R signal of the DSP initiates a conversion and conversion results are read from the LTC1273 using the following instruction: IN D, PA where D is Data Memory Address and PA is the PORT ADDRESS.
A16 A1 ADDRESS BUS
IS TMS320C25 READY R/W D16 D0
EN
ADDRESS DECODE LTC1273/75/76 CS BUSY RD
DATA BUS
D11 D0/8 HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 * F17
Figure 17. TMS320C25 Interface
MC68000 Microprocessor Figure 18 shows a typical interface for the MC68000. The LTC1273 is operating in the Slow Memory Mode. Assuming the LTC1273 is located at address C000, then the following single 16-bit MOVE instruction both starts a conversion and reads the conversion result: Move.W $C000,D0 At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DTACK so that the MC68000 is forced into a WAIT state. At the end of conversion, BUSY returns high and the conversion result is placed in the D0 register of the microprocessor.
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A23 A1 ADDRESS BUS AS MC68000 DTACK R/W D11 D0 DATA BUS EN ADDRESS DECODE LTC1273/75/76 CS BUSY RD D11 D0/8 HBEN ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 * F18
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Figure 18. MC68000 Interface
8085A/Z80 Microprocessor Figure 19 shows an LTC1273 interface for the Z80/8085A. The LTC1273 is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. A0 is used to assert HBEN so that an even address (HBEN = LOW) to the LTC1273 will start a conversion and read the low data byte. An odd address (HBEN = HIGH) will read the high data byte. This is accomplished with the single 16-bit LOAD instruction below. For the 8085A For the Z80 LHLD (B000) LDHL, (B000)
A15 A0
ADDRESS BUS
A0
MREQ Z80 8085A WAIT RD D7 D0
EN
ADDRESS DECODE
HBEN CS BUSY LTC1273/75/76 RD D7 D0/8
DATA BUS
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 * F19
Figure 19. 8085A and Z80 Interface
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current so it can be accurately driven by the unbuffered MUX. The CD4520 counter increments the MUX channel after each sample is taken. Figure 22 shows the acquisition time of LTC1275 vs the source resistance. For a 500 maximum "on" resistance of the CD4051, the acquisition time of the ADC is not greatly affected. For larger source resistances, modest increases in acquisition time must be allowed.
5V CD4051 VDD NO BUFFER REQUIRED D11 AIN LTC1275 8 INPUT CHANNELS 2.8V INPUT VARIES CS RD BUSY
* * *
This is a two byte read instruction which loads the ADC data (address B000) into the HL register pair. During the first read operation, BUSY forces the microprocessor to WAIT for the LTC1273 conversion. No WAIT states are inserted during the second read operation when the microprocessor is reading the high data byte. TMS32010 Microcomputer Figure 20 shows an LTC1273/TMS32010 interface. The LTC1273 is operating in the ROM Mode. The LTC1273 is mapped at a port address. The following I/O instruction starts a conversion and reads the previous conversion result into data memory. IN A,PA (PA = PORT ADDRESS) When conversion is complete, a second I/O instruction reads the up-to-date data into memory and starts another conversion. A delay at least as long as the ADC conversion time must be allowed between I/O instructions.
PA2 PA0 PORT ADDRESS BUS
DEN TMS32010
EN
ADDRESS DECODE LTC1273/75/76 CS
D11 D0
DATA BUS
ACQUISITION TIME (s)
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1273/75/76 * F20
Figure 20. TMS32010 Interface
MUXing with CD4051 The high input impedance of the LTC1273/LTC1275/ LTC1276 provides an easy, cheap, fast, and accurate way to multiplex many channels of data through one converter. Figure 21 shows a low cost CD4051 connected to the LTC1275. The LTC1275's input draws no DC input
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P OR DSP
LTC1273/75/76 * F21
VSS VEE A -5V
BC Q2 Q1
5V ENABLE CD4520 COUNTER Q0 RESET
Figure 21. MUXing the LTC1275 with CD4051
RD D11 D0/8 HBEN
4
3
RSOURCE AIN VIN LTC1275
2
1
500
0 10 100 1k SOURCE RESISTANCE () 10k
LTC1273/75/76 * F22
Figure 22. Acqusition Time of LTC1275 vs Source Resistance
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APPLICATI S I FOR ATIO U
A time domain view of the demodulation is shown in Figure 25. The top trace shows the 455kHz waveform modulated by a - 6dB, 5kHz signal. The bottom trace shows the demodulated signal produced by the LTC1275 reconstructed through a 12-bit DAC. The resultant frequency is 5kHz with a sample rate of 227.5kHz. There are roughly 45 points per cycle.
455kHz AM SIGNAL 1V/DIV DEMODULATED 5kHz OUTPUT
LTC1273/75/76 * F23
Demodulating a Signal by Undersampling with LTC1275 Figure 23 shows a 455kHz amplitude modulated input undersampled by the LTC1275. With a 227.5kHz sample rate, the converter provides a 100dB noise floor and 68dB distortion when digitizing the 455kHz AM input. Figure 24 shows an FFT of the AM signal digitized at 212.5kHz.
5V 227.5kHz SAMPLE RATE
455kHz AMPLITUDE MODULATED INPUT
RD AIN LTC1275 D11 D0
-5V
Figure 23. A 455kHz Amplitude Modulated Input Undersampled by the LTC1275
0 -10 -20 -30
AMPLITUDE (dB)
fSAMPLE = 212.5kHz fIN = 454.8kHz fMOD = 5.03kHz
-40 -50 -60 -70 -80 -90
-100 -110 0 20 40 60 80 FREQUENCY (kHz) 100 120
Figure 24. 455kHz Input Voltage Modulated by a 5kHz Signal
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DATA OUTPUT
1V/DIV
50s/DIV
LTC1273/75/76 * F27
Figure 25. 455kHz AM Signal Demodulated to 10.5 ENOBs
100ps Resolution Time Measurement with LTC1273 Figure 26 shows a circuit that precisely measures the difference in time between two events. It has a 400ns full scale and 100ps resolution. The start signal releases the ramp generator made up of the PNP current source and the 250pF capacitor. The circuit ramps until the stop signal shuts off the current source. The final value of the ramp represents the time between the start and stop events. The LTC1273 digitizes this final value and outputs the digital data.
LTC1273/75/76 * F24
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APPLICATI
65 1N457 2N5771 LM134 45.3 74HC03 1N457 45.3 74HC74 5V START D CLK CLR Q Q 1k 1N4148 10k 5V STOP D CLK CLR Q 5V Q 1k 100k 0.001F 1N4148 100pF 250pF POLYSTYRENE 620 20k AIN REFOUT VDD 12-BIT DATA OUTPUT
S I FOR ATIO
7V 65
1k 5V 10k 10pF
LTC1273/75/76 * F26
Figure 26. Time Measurement with the LTC1273
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PACKAGE DESCRIPTIO U
N Package 24-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
1.280* (32.512) MAX 24 23 22 21 20 19 18 17 16 15 14 13 .255 .015* (6.477 0.381) 1 .300 - .325 (7.620 - 8.255) .130 .005 (3.302 0.127) .020 (0.508) MIN .008 - .015 (0.203 - 0.381) 2 3 4 5 6 7 8 9 10 11 12 .045 - .065 (1.143 - 1.651) .065 (1.651) TYP
N24 0405
(
+.035 .325 -.015 +0.889 8.255 -0.381
)
.120 (3.048) MIN
.100 (2.54) BSC
.018 .003 (0.457 0.076)
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
SW Package 24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.030 .005 TYP N 24 23 22 21 .050 BSC .045 .005 .598 - .614 (15.190 - 15.600) NOTE 4 20 19 18 17 16
15
14
13
N .420 MIN .325 .005 NOTE 3 .394 - .419 (10.007 - 10.643)
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT .291 - .299 (7.391 - 7.595) NOTE 4 .010 - .029 x 45 (0.254 - 0.737)
0 - 8 TYP
1 .093 - .104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12 .037 - .045 (0.940 - 1.143)
.005 (0.127) RAD MIN
.009 - .013 (0.229 - 0.330) NOTE: 1. DIMENSIONS IN
NOTE 3 .016 - .050 (0.406 - 1.270)
.050 (1.270) BSC
.004 - .012 (0.102 - 0.305)
.014 - .019 (0.356 - 0.482) TYP
S24 (WIDE) 0502
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1273 LTC1275/LTC1276 RELATED PARTS
PART NUMBER LTC1272-3 LTC1278-4 LTC1278-5 LTC1403/LTC1403-1 LT1460 LT1790 LTC1860 LTC1864 DESCRIPTION 12-Bit, 250ksps ADC 12-Bit, 400ksps, Single Channel ADC 12-Bit, 500ksps, Single Channel ADC 12-Bit, 2.8Msps, Single Channel ADC Micropower Precision Series Reference Micropower Low Dropout Reference 12-Bit, 250ksps, Single Channel ADC 16-Bit, 250ksps, Single Channel ADC COMMENTS 5V Single Supply, Internal Reference, AD7572 Pinout 5V or 5V Supplies, 0V to 5V or 2.5V Input Range 5V or 5V Supplies, 0V to 5V or 2.5V Input Range 3V Single Supply, 14mW, 10-Pin MSOP Package 130A Supply Current, 10ppm/C, SOT-23 Package 60A Supply Current, 10ppm/C, SOT-23 Package 5V Single Supply, 4.25mW, 10-Pin MSOP Package 5V Single Supply, 4.25mW, 10-Pin MSOP Package
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24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0107 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 1993

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